ISA: LoongArch

LS3C5000 Specification

Key Features

- Loongson instruction set architecture (LoongArch® ) 
- High-end multi-way: up to 16 socket with 256-core CC-NUMA interconnection structure. 
- Excellent computing performance: measured over 900 points with SPEC CPU2006 result on 4 socket server.
- Efficient virtualization: Over 95% of KVM computing efficiency
- High-speed interconnection: Multi-level hierarchical cache coherence protocol for efficient local and cross-chip access. 
- High bandwidth of memory: 4 memory channels per socket, providing sufficient bandwidth.
- Supporting extended I/O: dual-bridge chipset support on multi-socket server



Peak computing speed


Number of cores


Processor core

64-bit superscalar LA464 cores; supporting LoongArch ISA; supporting 128/256-bit vector instructions; 4-issue out-of-order execution; 4 fixed-point units, 2 vector units, and 2 memory access units

High-speed cache

Each core includes a 64KB private L1 instruction cache and a 64KB private L1 data cache. Each core contains 256KB private L2 cache. All processor cores share a 32MB L3 cache.

Memory controller

four 72-bit DDR4-3200 controllers; supporting ECC

High-speed I/O

HyperTransport 3.0 I/O interface (HT0) and 3 coherent interconnect high-speed interfaces (HT1, HT2, and HT3)

Other I/O

1 SPI, 1 UART, 3 I2Cs, and 16 GPIO interfaces

Power management

supporting dynamic shutdown of the clocks of main modules; supporting dynamic frequency scaling in main clock domains; supporting dynamic voltage scaling in main voltage domains

Typical power consumption


LS3C5000 Manual

LS3C5000 Application