- Loongson instruction set architecture (LoongArch® )
- Measured single-core in SPEC CPU 2006 Base result over 26
- Measured memory bandwidth over 25 GB/s with DDR4-3200 interface
- Unified ecosystem compatibility: real-time binary translation supports of applications from different ISAs
- Fine-grained power management: Built-in power control core for dynamic voltage and frequency scaling
Peak computing speed
Number of cores
64-bit superscalar processor core LA464; Supporting LoongArch® instruction set architecture; Supporting 128/256-bit vector instructions;4-issue out-of-order execution;4 fixed-point units, 2 vector units, and 2 memory access units
Each processor core contains a 64KB private L1 instruction cache and a 64KB private L1 data cache; Each processor core contains a 256KB private L2 cache; All processor cores share a 16MB L3 cache.
Two 72-bit DDR4-3200 controllers; Supporting ECC
2 HyperTransport 3.0 controllers; Supporting Cache Coherent Non–Uniform Memory Access (CC-NUMA)
1 SPI, 1 UART, 2 I2Cs, 16 GPIO interfaces
Supporting dynamic shutdown of clocks of main modules; Supporting dynamic frequency scaling in main clock domains; Supporting dynamic voltage scaling in main voltage domains.
Typical power consumption