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ISA: LoongArch

LS2K0300/LS2K0301 Specification

Processor core

1×64-bit dual-issue superscalar LA264 cores, based on LoongArch

Frequency

1GHz

High-speed cache

32KB L1 instruction cache and 32KB L1 data cache, Supports ECC; 512KB L2 shared cache, Supports ECC

Memory controller

16-bit DDR4-1600 controllers; supporting ECC (LS2K0301 integrates 4Gb DDR4 memory chips)

High-Speed I/O

2×USB 2.0, 2×GMAC, 1×LCD display

Other I/O

1×I²S,4×CAN-FD,4×SPI,2×QSPI,2×eMMC,2×SDIO,1×LIO,8-lane ADC,4×I²C,10×UART,4×PWM,3 TIMER groups,106×GPIO,RTC,HPET,JTAG,etc.

Packaging

12mm×12mm FC-CSP package with 286 pins(2K0300); 15mm×13mm FC-CSP package with 264 pins(2K0301)

Power management

Supporting dynamic frequency scaling in processor core clock domains; supporting dynamic shutdown of the clocks of main modules

Typical power Consumption

<1W@1GHz(2K0300),<1.5W@1GHz(2K0301)

LS2K0300/LS2K0301 Manual

LS2K0300/LS2K0301 Application